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Synopsys’ Collaboration with Industry Consortium Yields Double Patterning Technology Models for Parasitic Extraction

IMTAB Group in IEEE-ISTO Ratifies Interconnect Technology Format Extensions for 20nm

MOUNTAIN VIEW, Calif., March 28, 2012--- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced that its collaboration with the members of the Interconnect Modeling Technical Advisory Board (IMTAB) of the IEEE Industry Standards and Technology Organization (IEEE-ISTO) has resulted in a parasitic variation modeling solution to address the effects of double patterning technology (DPT), targeted for use in 20-nanometer (nm) IC manufacturing. The new DPT model extensions will be available to the EDA and semiconductor industries through the open source licensed Interconnect Technology Format (ITF) version 2012.06 ratified by IMTAB members, including Apache Design – a subsidiary of ANSYS, GLOBALFOUNDRIES, NVIDIA, Synopsys and others (the full member list is available at